The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
During manufacturing of ultra-high density integrated circuits (UHDICs), such as certain memory chips, metal lines and vias are formed to provide various conductive connections. Pitch between metal lines and vias is typically the smallest pitch between conductive elements of the UHDICs. The metal lines and vias may be formed using a dual damascene process. During the dual damascene process masks are formed for the metal lines and the vias. The masks for the vias can overlay the masks for the metal lines. Due to processing errors, systematic shifts and/or noise, the masks for the vias may not be aligned with the masks for the metal lines. As a result, one or more vias may be spaced closer to one or more of the metal lines, thus further reducing a minimum pitch between metal lines and vias.
This mask layer-to-mask layer overlay error is illustrated by FIGS. 1A-2B, which show metal lines and respective vias. FIGS. 1A and 1B show two vias 100, 102 aligned with two metal lines 104, 106 in a direction in which the metal lines 104, 106 are extending, such that two opposing sides 108, 110 of each of the vias 100, 102 are aligned with two opposing sides 112, 114 of each of the metal lines. The vias 100, 102 are disposed along and between ends 116, 118 of the metal lines 104, 106. The two metal lines 104, 106 may be Vdd and Vss nets (or rails) and are in a same layer Mx. The first metal line 104 may be connected to a voltage supply and be at a voltage Vdd. The second metal line 106 may be connected to a reference terminal (or ground) and have a voltage Vss. The first via 100 may be connected as shown to an interconnect line (not shown), which may be in a layer Mx−1. The aligned metal lines 104, 106 and vias 100, 102 have an associated metal line-to-via pitch S (i.e., distance between each of the metal lines 104, 106 and a corresponding one of the vias 100, 102 that is connected to the other one of the metal lines 104, 106 metal line).
FIGS. 2A and 2B show two vias 200, 202 misaligned relative to two metal lines 204, 206. FIG. 2A shows the vias 200, 202 offset from the metal lines 204, 206 and having associated metal line-to-via pitch of S′. The metal lines 204, 206 are in a same layer Mx. The first via 200 may be connected to a voltage supply and be at a voltage Vdd. The second via 202 may be connected to a reference terminal (or ground) and have a voltage Vss. The first via 200 may be connected to an interconnect line (not shown), which may be in a layer Mx−1.
UHDICs are typically designed to minimize pitch between circuit elements. This includes minimizing spacing between metal lines and vias. The spacing between metal lines and vias may be set based on a photolithography resolution limit. Minimizing the spacing minimizes associated chip area. However, due to the above-stated mask layer-to-mask layer overlay error, the spacing may be further reduced in certain areas. In a deep sub-100 nanometer (nm) process, overlay of masks becomes a large portion of metal line to via edge placement error. Reduced spacing between Vdd and Vss metal lines and vias can result in a short between circuit elements and/or a breakdown over time of dielectric material between the metal lines and vias. A short can result in a functionality failure. A reliability issue exists if the dielectric between the circuit elements breakdown over time (referred to as a time dependent dielectric breakdown (TDDB)).